Piece-Wise-Linear Ramp ADC for CMOS Image Sensor and Calibration Techniques
نویسندگان
چکیده
In this paper, a 10-bit digital Correlated Double Sampling (CDS) high-speed CMOS Image Sensor designed in 65nm BSI technology for a 1.1μm pixel is proposed. The readout architecture has been developed to read a 13Mpix sensor (4248 x 3216) at 55frames/s, requiring a row time of 5.5μs. The readout is based on a Piece-Wise Linear (PWL) ramp generator implementing an I/C structure. Two innovative calibration techniques for output data linearization are investigated.
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